FPGA可编程逻辑器件芯片EP3SE50F484C4L中文规格书

The ns bits of the dma_periph register determine if a peripheral request interface issecure or non-secure.

Note:

The ns bits of the dma_periph register must be configured before the DMA isreleased from global reset.Related Information••

DMA Controller on page 119

System Manager Address Map and Register Definitions on page 172

12.3.1.2. NAND Flash Controller

The bootstrap control register (nand_bootstrap) modifies the default behavior ofthe NAND flash controller after reset. The NAND flash controller samples the bootstrapcontrol register bits when it comes out of reset.

The following nand_bootstrap register bits control configuration of the NAND flashcontroller:•

Bootstrap inhibit initialization bit (noinit)—inhibits the NAND flash controllerfrom initializing when coming out of reset, and allows software to program allregisters pertaining to device parameters such as page size and width.

Bootstrap 512-byte device bit (page512)—informs the NAND flash controller thata NAND flash device with a 512-byte page size is connected to the system.Bootstrap inhibit load block 0 page 0 bit (noloadb0p0)—inhibits the NAND flashcontroller from loading page 0 of block 0 of the NAND flash device during theinitialization procedure.

Bootstrap two row address cycles bit (tworowaddr)—informs the NAND flashcontroller that only two row address cycles are required instead of the defaultthree row address cycles.

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You can use the system manager's nand_l3master register to control the followingsignals:••••••

ARPROTAWPROTARDOMAINAWDOMAINARCACHEAWCACHE

These bits define the cache attributes for the master transactions of the DMA engine inthe NAND controller.

Note:

Register bits must be accessed only when the master interface is guaranteed to be inan inactive state.Related Information••

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NAND Flash Controller on page 190

System Manager Address Map and Register Definitions on page 172

12.System ManagerMNL-1100 | 2021.03.09

12.3.1.3. EMAC

You can program the emac_global register to select either emac_ptp_clk from theClock Manager or f2s_ptp_ref_clk from the FPGA fabric as the source of the IEEE1588 reference clock for each EMAC.

You can program the system manager's emac* register to control the EMAC's

ARCACHE and AWCACHE signals. These bits define the cache attributes for the mastertransactions of the DMA engine in the EMAC controllers.

Note:

Register bits must be accessed only when the master interface is guaranteed to be inan inactive state.

The phy_intf_sel bit is programmed to select between a GMII (MII), RGMII or RMIIPHY interface when the peripheral is released from reset. The ptp_ref_sel bit in theemac* registers selects if the timestamp reference is internally or externally

generated. The ptp_ref_sel bit must be set to the correct value before the EMACcore is pulled out of reset.

Note:

EMAC0 must be set to internal timestamp.Related Information••

Clock Manager on page 154

Ethernet Media Access Controller on page 314

12.3.1.4. USB 2.0 OTG Controller

The usb*_l3master registers in the system manager control the HPROT and HAUSERfields of the USB master port of the USB 2.0 OTG Controller.

Note:

Register bits should be accessed only when the master interface is guaranteed to be inan inactive state.Related Information

USB 2.0 OTG Controller on page 388

12.3.1.5. SD/MMC Controller

The sdmmc_l3master register in the system manager controls the HPROT andHAUSER fields of the SD/MMC master port.

Note:

Register bits should be accessed only when the master interface is guaranteed to be inan inactive state.

You can program software to select the clock’s phase shift for cclk_in and

sdmmc_smplsel by setting the drive clock phase shift select (drvsel) and sampleclock phase shift select (smplsel) bits of the sdmmc register in the system manager.Related Information

SD/MMC Controller on page 226

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12.System ManagerMNL-1100 | 2021.03.09

12.3.1.6. Watchdog Timer

The system manager controls the watchdog timer behavior when the CPUs are indebug mode. The system manager sends a pause signal to the watchdog timersdepending on the setting of the debug mode bits of the L4 watchdog debug register(wddbg). Each watchdog timer built into the MPU system complex is paused when itsassociated CPU enters debug mode.Related InformationWatchdog Timers on page 485

12.3.2. FPGA Interface Enables

The system manager can enable or disable interfaces between the FPGA and HPS.

Note:

Ensure that the FPGA is configured before enabling the interfaces and that allinterfaces between the FPGA and HPS are inactive before disabling them.

You can program the FPGA interface enable registers (fpgaintf_en_*) to enable/disable the following interfaces between the FPGA and HPS:•••••••••

Boundary scan interfaceDebug interfaceTrace interface

System Trace Macrocell (STM) interfaceCross-trigger interface (CTI)NAND interfaceSD/MMC interfaceSPI Master interfaceEMAC interfaces

12.3.3. ECC and Parity Control

The system manager can mask the ECC interrupts from each of the following HPSmodules with ECC-protected RAM:••••••••

MPU L2 cache data RAMOn-chip RAM

USB 2.0 OTG controller (USB0 and USB1) RAMEMAC (EMAC0, EMAC1, and EMAC2) RAMDMA controller RAMNAND flash controller RAMSD/MMC controller RAMDDR interfaces

System manager provides combined ECC status and interrupt from each of these HPSmodules. Each modules generates single or double bit error, which the systemmanager combines to generate interrupts.

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