MC100EP52DT资料

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MC10EP52, MC100EP523.3V / 5V󰀂ECL DifferentialData and Clock D Flip−Flop

The MC10EP/100EP52 is a differential data, differential clock Dflip−flop. The device is pin and functionally equivalent to the EL52device.

Data enters the master portion of the flip−flop when the clock isLOW and is transferred to the slave, and thus the outputs, upon apositive transition of the clock. The differential clock inputs of theEP52 allow the device to also be used as a negative edge triggereddevice.

The EP52 employs input clamping circuitry so that under open inputconditions (pulled down to VEE) the outputs of the device will remainstable.

The 100 Series contains temperature compensation.

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MARKING DIAGRAMS*881SO−8D SUFFIXCASE 7511HEP52ALYW18KEP52ALYW•••••••

330 ps Typical Propagation DelayMaximum Frequency u 4 GHz Typical

PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 VNECL Mode: VCC = 0 V with VEE = −3.0 V to −5.5 VOpen Input Default StateSafety Clamp on Inputs

Q Output Will Default LOW with Inputs Open or at VEE

H= MC10K= MC100A= Assembly LocationL= Wafer LotY= YearW= Work Week81TSSOP−8DT SUFFIXCASE 948R8HP52ALYW118KP52ALYW*For additional marking information, refer to Application Note AND8002/D.ORDERING INFORMATION

See detailed ordering and shipping information in the packagedimensions section on page 7 of this data sheet.

June, 2004 − Rev. 3

Publication Order Number:

MC10EP52/D

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MC10EP52, MC100EP52

Table 1. PIN DESCRIPTION

PINCLK*, CLK*D2DD*, D*7Flip-FlopCLK

36QQ

Q, QVCCVEEFUNCTIONECL Clock InputsECL Data InputECL Data OutputsPositive SupplyNegative SupplyD18VCC

*Pins will default LOW when left open.Table 2. TRUTH TABLE

CLK45VEE

DLH

CLKZZ

QLH

Figure 1. 8−Lead Pinout (Top View) and Logic Diagram

Z = LOW to HIGH Transition

Table 3. ATTRIBUTESCharacteristicsInternal Input Pulldown ResistorInternal Input Pullup ResistorESD ProtectionHuman Body ModelMachine ModelCharged Device ModelValue75 kWN/A> 4 kV> 200 V> 2 kVLevel 1UL 94 V−0 @ 0.125 in155 DevicesMoisture Sensitivity, Indefinite Time Out of Drypack (Note 1)Flammability RatingTransistor CountMeets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test1.For additional information, see Application Note AND8003/D.Oxygen Index: 28 to 34http://onsemi.com

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MC10EP52, MC100EP52

Table 4. MAXIMUM RATINGS

SymbolVCCVEEVIIoutIBBTATstgqJAqJCqJAqJCParameterPECL Mode Power SupplyNECL Mode Power SupplyPECL Mode Inut VoltagePECL Mode Input VoltageNECL Mode Input VoltageOutput CurrentVBB Sink/SourceOperating Temperature RangeStorage Temperature RangeThermal Resistance (Junction to Ambient)Thermal Resistance (Junction to Case)Thermal Resistance (Junction to Ambient)Thermal Resistance (Junction to Case)0 lfpm500 lfpmStandard Board0 lfpm500 lfpmStandard BoardSOIC−8SOIC−8SOIC−8TSSOP−8TSSOP−8TSSOP−8Condition 1VEE = 0 VVCC = 0 VVEE = 0 V 0 VVCC = 0 VContinuousSurgeVI v VCCVI w VEECondition 2Rating6−66−650100± 0.5−40 to +85−65 to +15019013041 to 4418514041 to 44UnitVVVVmAmAmA°C°C°C/W°C/W°C/W°C/W°C/W°C/WTsolWave Solder<2 to 3 sec @ 248°C265°CMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limitvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.

Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)−40°CSymbolIEEVOHVOLVIHVILVIHCMRIIHIILCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 3)Output LOW Voltage (Note 3)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 4)Input HIGH CurrentInput LOW Current0.5Min2621651365209013652.0Typ3422901490Max4424151615241516903.3Min2622301430215514302.025°CTyp3523551555Max4524801680248017553.3Min2822901490221514902.085°CTyp3724151615Max4725401740254018153.3UnitmAmVmVmVmVV1500.51500.5150mAmANOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limitvalues are applied individually under normal operating conditions and not valid simultaneously.

2.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.3.All loading with 50 W to VCC − 2.0 V.

4.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

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MC10EP52, MC100EP52

Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)−40°CSymbolIEEVOHVOLVIHVILVIHCMRIIHIILCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 6)Output LOW Voltage (Note 6)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 7)Input HIGH CurrentInput LOW Current0.5Min2638653065379030652.0Typ3439903190Max4441153315411533905.0Min2639303130385531302.025°CTyp3540553255Max4541803380418034555.0Min2839903190391531902.085°CTyp3741153315Max4742403440424035155.0UnitmAmVmVmVmVV1500.51500.5150mAmANOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

5.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.6.All loading with 50 W to VCC − 2.0 V.

7.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 8)−40°CSymbolIEEVOHVOLVIHVILVIHCMRIIHIILCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 9)Output LOW Voltage (Note 9)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 10)Input HIGH CurrentInput LOW Current0.5Min26−1135−1935−1210−1935VEE+2.0Typ34−1010−1810Max44−885−1685−885−16100.0Min26−1070−1870−1145−1870VEE+2.025°CTyp35−945−1745Max45−820−1620−820−15450.0Min28−1010−1810−1085−1810VEE+2.085°CTyp37−885−1685Max47−760−1560−760−14850.0UnitmAmVmVmVmVV1500.51500.5150mAmANOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

8.Input and output parameters vary 1:1 with VCC.9.All loading with 50 W to VCC − 2.0 V.

10.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

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MC10EP52, MC100EP52

Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 11)−40°CSymbolIEEVOHVOLVIHVILVIHCMRCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 12)Output LOW Voltage (Note 12)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 13)Input HIGH CurrentInput LOW Current0.5Min2621551355207513552.0Typ3422801480Max4424051605242016753.3Min2621551355207513552.025°CTyp3522801480Max4524051605242016753.3Min2821551355207513552.085°CTyp3722801480Max4724051605242016753.3UnitmAmVmVmVmVVIIHIIL1500.51500.5150mAmANOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

11.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.12.All loading with 50 W to VCC − 2.0 V.

13.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 14)−40°CSymbolIEEVOHVOLVIHVILVIHCMRCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 15)Output LOW Voltage (Note 15)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 16)Input HIGH CurrentInput LOW Current0.5Min2638553055377530552.0Typ3439803180Max4441053305412033755.0Min2638553055377530552.025°CTyp3539803180Max4541053305412033755.0Min2838553055377530552.085°CTyp3739803180Max4741053305412033755.0UnitmAmVmVmVmVVIIHIIL1500.51500.5150mAmANOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

14.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.15.All loading with 50 W to VCC − 2.0 V.

16.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

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MC10EP52, MC100EP52

Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 17)−40°CSymbolIEEVOHVOLVIHVILVIHCMRCharacteristicPower Supply CurrentOutput HIGH Voltage (Note 18)Output LOW Voltage (Note 18)Input HIGH Voltage (Single−Ended)Input LOW Voltage (Single−Ended)Input HIGH Voltage Common ModeRange (Differential Configuration)(Note 19)Input HIGH CurrentInput LOW Current0.5Min26−1145−1945−1225−1945VEE+2.0Typ34−1020−1820Max44−895−1695−880−16250.0Min26−1145−1945−1225−1945VEE+2.025°CTyp35−1020−1820Max45−895−1695−880−16250.0Min28−1145−1945−1225−1945VEE+2.085°CTyp37−1020−1820Max47−895−1695−880−16250.0UnitmAmVmVmVmVVIIHIIL1500.51500.5150mAmANOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

17.Input and output parameters vary 1:1 with VCC.18.All loading with 50 W to VCC − 2.0 V.

19.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differentialinput signal.

Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 20)

−40°CSymbolVOUTpptPLH,tPHLtStHtJITTERVPPtrtfCharacteristicOutput Voltage Amplitude @ 3.0 GHz(Figure 2)Propagation Delay to Output DifferentialCLK, CLK−>Q, QSetup TimeHold TimeCLOCK Random Jitter (RMS)(Figure 2)Input Voltage Swing(Differential Configuration)Output Rise/Fall Times(20% − 80%) Q, Q1502505000.2800112001503003502805000.2800112001503303803105000.280011200360410pspsmVps701101708012018090130200Min630Typ750MaxMin61025°CTyp730MaxMin52085°CTyp640MaxUnitGHzpsNOTE:Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuitboard with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.

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MC10EP52, MC100EP52

0.9

5 V0.8VOUTpp (mV)0.70.60.50.40.30.20.10.00.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

3.3 VFREQUENCY (MHz)

Figure 2. Fmax Typical

QDriverDeviceQZo = 50 WDReceiverDeviceZo = 50 W50 W50 WDVTT

VTT = VCC − 2.0 V

Figure 3. Typical Termination for Output Driver and Device Evaluation(See Application Note AND8020/D − Termination of ECL Logic Devices.)

ORDERING INFORMATION

DeviceMC10EP52DMC10EP52DR2MC100EP52DMC100EP52DR2MC10EP52DTMC10EP52DTR2MC100EP52DTMC100EP52DTR2PackageSO−8SO−8SO−8SO−8TSSOP−8TSSOP−8TSSOP−8TSSOP−8Shipping†98 Units / Rail2500 Tape & Reel98 Units / Rail2500 Tape & Reel100 Units / Rail2500 Tape & Reel100 Units / Rail2500 Tape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

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MC10EP52, MC100EP52

Resource Reference of Application Notes

AN1405/DAN1406/DAN1503/DAN1504/DAN1568/DAN1642/DAND8001/DAND8002/DAND8020/DAND8066/DAND8090/D

−ECL Clock Distribution Techniques−Designing with PECL (ECL at +5.0 V)−ECLinPSt I/O SPiCE Modeling Kit−Metastability and the ECLinPS Family−Interfacing Between LVDS and ECL−The ECL Translator Guide−Odd Number Counters Design−Marking and Date Codes−Termination of ECL Logic Devices−Interfacing with ECLinPS

−AC Characteristics of ECL Devices

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MC10EP52, MC100EP52

PACKAGE DIMENSIONS

SO−8D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751−07ISSUE AB

NOTES:

1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A AND B DO NOT INCLUDEMOLD PROTRUSION.

4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.

5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6.751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

MILLIMETERSMINMAX4.805.003.804.001.351.750.330.511.27 BSC0.100.250.190.250.401.270 _8 _0.250.505.806.20

INCHES

MINMAX0.1890.1970.1500.1570.0530.0690.0130.0200.050 BSC0.0040.0100.0070.0100.0160.0500 _8 _0.0100.0200.2280.244

−X−A85B1S40.25 (0.010)MYM−Y−GKC−Z−HD0.25 (0.010)

MSEATINGPLANENX 45_0.10 (0.004)MJZY

SDIMABCDGHJKMNS

RECOMMENDED FOOTPRINT

1.520.0607.00.2754.00.1550.60.0241.2700.050SCALE 6:1

mmǓǒinches

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MC10EP52, MC100EP52

TSSOP−8DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R−02

ISSUE A

8x REFKNOTES:

1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.

2.CONTROLLING DIMENSION: MILLIMETER.

3.DIMENSION A DOES NOT INCLUDE MOLD FLASH.PROTRUSIONS OR GATE BURRS. MOLD FLASHOR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.

4.DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED 0.25 (0.010)PER SIDE.

5.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.

6.DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE −W−.

MILLIMETERSMINMAX2.903.102.903.100.801.100.050.150.400.700.65 BSC0.250.404.90 BSC0 6 __INCHESMINMAX0.1140.1220.1140.1220.0310.0430.0020.0060.0160.0280.026 BSC0.0100.0160.193 BSC0 6 __0.15 (0.006)TUS2X0.10 (0.004)L/2815MTUSVSLPIN 1IDENT4B−U−0.25 (0.010)M0.15 (0.006)TUSA−V−FDETAIL EC0.10 (0.004)−T−SEATINGPLANEDGDETAIL E−W−DIMABCDFGKLMECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Alloperating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rightsnor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicationsintended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyerpurchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or deathassociated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an EqualOpportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll FreeUSA/CanadaJapan: ON Semiconductor, Japan Customer Focus Center2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051Phone: 81−3−5773−3850http://onsemi.com10MC10EP52/D

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