CMOS FIELD-PROGRAMMABLE GATE ARRAYS
SRFS001 F -D3864, DECEMBER 1989 -REVISED FEBRUARY 1993
ordering info『mation
Configurations of the TPC 10 Series devices can be ordered using the pa同numbersin the examples below.
Commercial and industrial versions can be ordered as follows:
EXAMPLE PREFIX
－”
DEVICE TYPE 101 O= 1200 Equivalent Gate Array 1 020 = 2000 Equivalent Gate Array DEVICE REVISION
A = Tl 1.2-µm CMOS Technology B = Tl 1.0-µm CMOS Technology
…
叮」A FN-068 C 1
l二－……T
l
』－
1onal)
I
I
TEMPERATURE RANGE
C = 0。Ct70。cI = -40。Cto 85。C
。
」－
DEVICE PINS 044 = 44 pins 068 = 68 pins 084 = 84 pins 100 = 100 pins
PACKAGE TYPE
FN = Plastic leaded chip carrier VE = Plastic quad flat package
Military versions can be ordered as follows:
EXAMPLE -PREFIX
DEVICE TYPE 1010 = 1200 Equivalent Gates 1020 = 2000 Equivalent Gates
M GB 84 B -1
…
η」DEVICE REVISION
A= Tl 1.2-µm CMOS Technology
GB= Ceramic pin grid array HT = Ceramic quad flat package HFG = Ceramic quad flat package
with nonc。nductivetie bar TEMPERATURE RANGE M = -55。Cto 125。C
DEFENSE ELECTRONIC SYSTEM CENTER (DESC) NUMBER
DESC AVAILABLE
DEVICE NAME NUMBER PRCESSING
5962-9096401 M Class B TPC1010AM
5962-9096501 M Class BTPC1020AM
Space Equivalent
。
macro library
The TPC10 Series is supported by a macro lib『aryof more than 250 hardwired and soft macro functions. The macros range from primitive logic gates to MSl-level complex functions such as counters, decoders, and comparators. The hardwired macro characteristics are p「ovidedin the electrical and switching characteristics. The software macros have characteristics simila「tothe components of the macro but need the place and route data back annotated into the design to establish actual performance.
The FPGA logic『nod1』leimplements logic functions with inverted inputs as efficiently as noninverted inputs, without an increase in propagation delay. By taking advantage of the various combinations of input polarity, the use of separate inverters can be virtually eliminated.
TPC10 SERIES
CMOS FIELD-PROGRAMMABLE GATE ARRAYS
SRFS001 F -D3864, DECEMBER 1989 -REVISED FEBRUARY 1993
ordering info『mation
Configurations of the TPC 10 Series devices can be ordered using the pa同numbersin the examples below.
Commercial and industrial versions can be ordered as follows:
EXAMPLE PREFIX
－”
DEVICE TYPE 101 O= 1200 Equivalent Gate Array 1 020 = 2000 Equivalent Gate Array DEVICE REVISION
A = Tl 1.2-µm CMOS Technology B = Tl 1.0-µm CMOS Technology
…
叮」A FN-068 C 1
l二－……T
l
』－
1onal)
I
I
TEMPERATURE RANGE
C = 0。Ct70。cI = -40。Cto 85。C
。
」－
DEVICE PINS 044 = 44 pins 068 = 68 pins 084 = 84 pins 100 = 100 pins
PACKAGE TYPE
FN = Plastic leaded chip carrier VE = Plastic quad flat package
Military versions can be ordered as follows:
EXAMPLE -PREFIX
DEVICE TYPE 1010 = 1200 Equivalent Gates 1020 = 2000 Equivalent Gates
M GB 84 B -1
…
η」DEVICE REVISION
A= Tl 1.2-µm CMOS Technology
GB= Ceramic pin grid array HT = Ceramic quad flat package HFG = Ceramic quad flat package
with nonc。nductivetie bar TEMPERATURE RANGE M = -55。Cto 125。C
DEFENSE ELECTRONIC SYSTEM CENTER (DESC) NUMBER
DESC AVAILABLE
DEVICE NAME NUMBER PRCESSING
5962-9096401 M Class B TPC1010AM
5962-9096501 M Class BTPC1020AM
Space Equivalent
。
macro library
The TPC10 Series is supported by a macro lib『aryof more than 250 hardwired and soft macro functions. The macros range from primitive logic gates to MSl-level complex functions such as counters, decoders, and comparators. The hardwired macro characteristics are p「ovidedin the electrical and switching characteristics. The software macros have characteristics simila「tothe components of the macro but need the place and route data back annotated into the design to establish actual performance.
The FPGA logic『nod1』leimplements logic functions with inverted inputs as efficiently as noninverted inputs, without an increase in propagation delay. By taking advantage of the various combinations of input polarity, the use of separate inverters can be virtually eliminated.
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