Performance improvement of a write instruction of

专利名称：Performance improvement of a write

instruction of a non-inclusive hierarchicalcache memory unit

发明人：Jin Chin Wang,Maciek P. Kozyrczak申请号：US10041932申请日：20020107

公开号：US20020174304A1公开日：20021121

专利附图：

摘要：Described is a data processing system including a processor, a plurality ofcaches, and main memory, the secondary caches being implemented as being non-

inclusive, i.e., the lower order caches not storing a superset of the data stored in the nexthigher order cache. The non-inclusive cache structure provides increased flexibility in thestorage of data. The operation of a write request operation when the target data line isnot found in the primary cache. By using the dirty bit associated with each data line, theinteraction between the processor and the primary cache can be reduced. By using theinvalidity bit associated with each data line, the interaction between the processor andthe primary cache can be reduced.

申请人：WANG JIN CHIN,KOZYRCZAK MACIEK P.

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